Design and Analysis of an Optimized Approximate Adder
Adders are one of the key components of arithmetic circuits in a system and their throughput affects the overall performance of the system. Approximation can increase performance with a simplified or inaccurate circuit in application contexts, where the accuracy can be relaxed. In applications, exploiting the tradeoff between the hardware has tremendous potential to improve the efficiency of integrated systems. However accuracy varies according to the applications, the digital hardware computational blocks or adders with different structures are designed to compute the precise the results. In this paper , 8-bit approximate adder is proposed systematically mainly focusing on the mean square error.it provides tradeoff between the hardware and accuracy. For different configuration adders simulation is performed in modelsim and synthesized in design compiler tool by synopsis with 28nm library. The synthesis is carried out for 8-bit exact adder, lower part constant OR adder, and proposed adder on the same platform. The proposed adder improves the mean square error by 7.925% when compared with previous architecture.