Design and Performance Analysis of Low-Power High-Speed Hybrid Logic Style Full Adders

Abstract

:-  In VLSI digital system, such as a computer or data processing control or micro-processors or digital signal processing systems contain essential blocks that perform arithmetic operations like addition, subtraction, multiplication and division. Among all, the basic operation is addition since subtraction is 2’s compliment form of addition, multiplication is basically repetitive addition and division is frequent subtraction. Therefore, reducing power consumption in Full adder in turn reduces the overall power consumption of entire system. In this regard the need of an effective adder is equitably high. This paper presents enhanced characteristics and performance of 1-bit Hybrid logic style Full Adder structures. The key objective of the design is to achieve a Low Power, High Speed and Energy efficient hybrid logic style Full Adder structures. In prior to design, performance comparison is carried out with several existing traditional Adder structures in 180nm and 90nm technology. The proposed circuits simulation results are compared with most popular 28T-Conventional CMOS FA structure in gpdk 180nm MOS technology using Cadence Virtuoso. The results evidently signify 54.26% Power improvement, 74.82% delay improvement and 88.49% PDP improvement.