DESIGN OF DIFFERENT STAGES OF CURRENT STARVED VOLTAGE CONTROLLED OSCILLATOR FOR PLL IN CMOS 180nm TECHNOLOGY.

Abstract

This work describes the design of 7,9,11 stages of CSVCO for PLL in CMOS 180nm technology. The controlled voltage of VCO is 0.5 to 3.3 V for high frequency range. PLLs are common applications of voltage controlled oscillators. CSVCO consists of cascaded inverters like in ring oscillators. A ring oscillator consists of an odd number of stages of inverters forming a feedback circuit. The output frequency is the replica of the applied voltage. The power supply used for CSVCO is 1.8 V. For simulation work Virtuoso Analog Design Environment tool of CADENCE is used.