Whale and Grey Wolf Optimization Algorithms for Test Scheduling of System-on-Chip

Abstract

In this paper, meta-heuristic optimization algorithms are used to minimize the test time of System-on-Chip (SoC). SoC is a single die with millions of transistors. The complexity of the SoC is much higher concerning the varying nature of core architecture. Testing an SoC is a complex, time consuming, and expensive process. Whale and Grey Wolf Optimization algorithms are used to minimize the test time. The effectiveness of the two optimization algorithms is evaluated by testing its scheduling time in p22810 and d695 benchmark circuits. To quantify the effectiveness of the Whale and Grey Wolf Optimization techniques, the scheduling time of these algorithms is compared with various optimization algorithms. The testing time of d695 benchmark circuit is reduced to 62%, 88%, 32%, 46%, 51%, 57%, 4%, and 2.5% compared to Modified ACO, ACO, Modified ABC, ABC, Modified Firefly, Firefly, BAT and GWO when WOA is used.  For the p22810 benchmark circuit, WOA testing time reduced to 97%, 98%, 31%, 47%, 64%, 68%, 4%, and 2% when compared with the same set of algorithms