An Efficient Wear leveling for Hybrid Cache Using Periodic Boundary Cellular Automata

Abstract

Future many-core chip multiprocessors (CMPs) are evolved alongside multi-programmed environment. Memory bandwidth limit and complex off-chip interconnect enforces a large-sized on-chip cache in CMPs. Durable SRAM (DRAM) cache occupies appreciable chip floor with increased power budget. However, high density nonvolatile memory (NVM) provides area shrinkage, low cost & ultra-low leakage power. But it is limited by cell endurance, write latency & write energy. Hybrid cache with NVM and SRAM (DRAM) therefore, can give two-fold performance enhancement. But it needs to be equipped with technology specific read and/or write management policies for reliable operation. Uneven workload distribution or malicious attacks are considered as the two main reasons of repetitive writes triggering early cell failure, limiting chip lifetime. Wear leveling has become a traditional method of reducing write-stress through remapping or avoiding redundant writes. Swear is a unique spatial locality aware read and write policy intended for hybrid cache to optimize cache utilization. The proposed novel runtime, cost-effective, less space-hungry, micro-architectural design solution is developed around the theory of Cellular automata (CA). Nonuniform Periodic Boundary CA is synthesized for Density classification task to identify the remapping zone (contiguous memory blocks) from the learning of memory access pattern. Simple algebraic method is used in zone-based interset & intraset remapping to build a durable cache.