A small RISC CPU implementation inspired on the Post's Machine

Abstract

A RISC architecture for the practical implementation of a small central processing unit (CPU) is proposed on the basis of an improved and updated Post's Machine. The Post’s Machine is similar to the Turing one, but with a more compact instruction set, which allows us to count on a general-purpose computer. The logical design of the digital system was developed by means of the Register Transfer Level (RTL) methodology, coded with VHDL language and implemented on a FPGA with a low-cost Basys 3 development board. It was showed that it is possible to build, with relatively limited resources, a basic RISC microprocessor for general purposes.

Keywords- Post's Machine; RISC architecture ; RTL implementation; CPU design.