Double Throughput CNTFET Based Dual Edge Triggered Flip Flop Design for Ultra-Low Voltage Applications
Implementation and optimization of power efficient sequential logic blocks in modern day VLSI becomes a crucial challenge. Especially, when going deeper into the submicron region there are many constraints affecting power dissipation and performance of clock storage elements (CSE's). Delay (D) flip flops are basic building blocks of clock storage elements. In this paper a detail investigation which mainly focuses on the exploration of a set of well-known dual edge triggered energy efficient D flip flop designs is reported. After that a new D flip flop design is proposedby the insertion of stack transistors into pull down network for minimum power delay performance. This flip flop structure is implemented using dual chirality concept. Extensive simulation has been done to examine the competency of the proposed design under different test conditions using 32nm CNTFET model. It is seen that CNTFET has all required features like high mobility near ballistic transport, large current carrying capacity as compared to conventional MOSFETs. Parametric variation in pitch and diameter, temperature, switching activity and supply voltage helps to evaluate propagation delay of the proposed D flip flop design. The result reported in this paper shows that average power gets reduced by 64% at 0.9voltfor 2GHz frequency and 1fF clock load capacitance.