Performance Analysis of Transistor Clamped Nine Level Inverters for Harmonics Reduction

Authors

  • S. Usha , T.M. Thamizh Thentral , A. Geetha , Pranjul Mani Dubey , Nishant Gunasekaran , Akanksha Lal

Abstract

This paper offerings a poly phase cascaded multilevel inverter employing a six bridge power cells for obtaining a
three phase, nine level output. A five-level transistor clamped H bridge configuration is used. To accomplish a stable
power supply for the power cells, a multicarrier pulse width modulation technique is used. To balance the capacitor
voltage, phase shift pulse width modulation is used. The obtained output voltage harmonics were analyzed with LC
filter and without filter.

Published

2020-03-31

Issue

Section

Articles