Hardware Acceleration Design Methodology for DSP Applications

Authors

  • Swati Sanjay Patil, Arun Kumar G., M. H. Nerkar

Abstract

Designers of Digital Signal Processing (DSP) systems are facing challenge of bringing enhanced processing capacity to compute complex DSP functions. A new computing paradigm called Reconfigurable Computing (RC) brings the phenomenon of reconfiguration of coprocessor for application without design of new application specific digital signal processor. Reconfigurable Computing can utilize Field Programmable Gate Array (FPGA) as computing platform to reconfigure coprocessor for user defined applications. This article will demonstrate various architectural approaches for development of co-processors that integrate with standard DSP computing architectures. Reconfiguration of coprocessors i.e. embedded soft processors or customized processor can be made in FPGA and integrated with off-the-shelf processors for complex DSP applications. The proposed methodology has been demonstrated through an implementation of embedded soft processor and a co-processor for DSP applications on FPGA Device. The methodology includes software profiling to estimate performance specifications and identify co-processor for best fit of functions. Finally, a parallelism through hardware/software integration methodology has been proposed and cases studies were shown for complete co-processor development of real life solution. The proposed methodologies could utilize standard tools and components that are applicable to many applications where signal processing performance requirements are driving up the cost and risk of system implementation.

Published

2020-02-29

Issue

Section

Articles