Low Power and High-Speed Novel Hybrid Full Adder based on TG & Swing Restored Transmission Switch (SWTS) Logic

Authors

  • Mr.Venkat Subbarao.Manchala, Dr.S.Ramesh. M.E, Ph.D.

Abstract

This paper explores Novel Hybrid full Adder (HFA) was formed based on Swing restored
Transmission gate switch (SWTG) and Transmission gate (TG) logic as a function of MUX, which has a
property of high speed and less short circuit path. This circuit has been compared to all the exited full Adder
designs such as Complementary metal-oxide-semiconductor (CMOS), Transmission Gate (TG) logic,
Transmission function Adder (TFA) logic, Gate diffusion input (GDI) logic, Self-Energy Recovery full
adder (SERF) logic, Complementary pass transistor logic (CPL), 6T – Pass Transistor (PTL) logic, Hybrid
full adder (HFA) Design with Positive Feedback. The above mentioned all Full Adder designs consist of
merits and demerits The primary goal of designing hybrid full adder(HFA) is to acquire low power, high
speed with full swing as well as good driving capability. We observed the simulation results in cadence
virtuoso 45nm, 90nm, and 180 nm technologies at a frequency of 1 GHz and tabulated values. The circuit
evaluation measured that power 1.385uw, delay 35.353p, and PDP 0.0485f joules were calculated in 45nm
technology. As the results postulated that the proposed design has a feature of low power consumption and
high speed of operation at high frequency (1GHz). Which has the superior advantage of good drive
capability and this design is well suited for high speed of operations Arithmetic logic unit (ALU)
operations.

Published

2020-02-28

Issue

Section

Articles