Low Power Tspc Flip Flop Design Based On Logic Reduction Schemes

Abstract

In this paper, a low power true single phase clocking flip-flop (TSPCFF) design achieved using only 18 transistors is proposed. The design follows a master and slave based on logic structure and hybrid design consists of both static CMOS logic and complementary pass transistor logic (CPL). This design has been developed with the main objective of lowering the clock signal loading. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high speed, low power and delay performance. Despite its circuit simplicity, no node floating is left during the operation to avoid leakage power consumption. In this paper, the parameters of six FF designs were compared like transistor sizes, average power, power delay product (PDP), Clock to Q (CQ) delay and Data to Q (DQ) delay. These designs perform under same voltage is 1 V and switching activity 12.5%. The simulations are performed in gpdk90nm technology using cadence virtuoso software tool.