An Innovative Approach For The Designing Of 4-Bit Arithmetic Logic Unit Using Full- Swing Gdi To Reduce Power Consumption

Authors

  • N. Hari priya, M. Madhusudhan Reddy

Abstract

In the past, during the desktop PC era, VLSI design’s primary goal was to optimize the speed of the real-time computational functions such as gaming, video compressing, and graphics. Due to that, we now have semiconductor ICs that can integrate various graphical processing units and signal processing modules that have the ability to fulfill our demands for entertainment and computation. While these design efforts have achieved the real-time computation power, they have not addressed the increasing need of portable devices such as mobile phones that are capable enough to carry the same complex operations without consuming as much power. The rising demand for portable and even wearable electronic devices for communication, computing, and entertainment has necessitated longer battery life, lower power consumption, and lesser device weight. Considering this, there seems a need to develop a solution that can make use of low voltage and low power design techniques. Now that power consumption is also considered as an important criterion in VLSI design, the design space might get expanded, thus adding to the complexity of the already significant tasks. In order to create an ideal solution for this problem, low power design has to be considered as a crucial factor. In this project we are designing a 4-bit low power consuming Arithmetic and Logical Unit (ALU) which consists of a 2x1 multiplexer 4x1 multiplier and a full adder which consumes less power. In this system we are reducing the power dissipation by decreasing the count of the transistors and reduce the area. We are using a Full swing GDI technique to reduce the count of the transistors.

Published

2020-10-16

Issue

Section

Articles