A High-Speed Low-Power SAR ADC for Wireless Transceiver

Authors

  • Fan He* , Donglin Cheng, Lei Qiao

Abstract

In this paper, a special SAR ADC structure with high power consumption efficiency is adopted.
A Flash ADC is used to realize rough conversion, and then a SAR ADC is used for fine conversion. The
following measures are adopted in ADC design: full dynamic comparators are adopted to reduce power
consumption. A part of the capacitors in CDAC are divided into two small capacitors of equal size. During
sampling, the bootstrap switch is used, so that the transistor's on-resistance does not change with the change
of the input signal, so as to enhance the linearity of ADC, and furthermore realize the high-speed and lowpower circuit architecture of SAR ADC. The current consumption is only 4mA and the SNDR is 61dB under
the premise of supply voltage of 1.2V and a sampling rate at 150MS/s

Published

2020-01-31

Issue

Section

Articles