DCVS design and analysis of the LFSR using feedback polynomial function for its low-power and reduced area overhead

Authors

  • Vishnupriya Shivakumar, C. Senthilpari, Zubaida Yusoff

Abstract

Linear Feedback shift register (LFSR) used as a pseudo-random pattern generator in the BIST designs. Differential Cascode Voltage Switch (DCVS) is the well-known high-speed TTL logic technique. Since it has complementary outputs with a reduced number of transistor designs for generating the maximum length of pseudo-random patterns. Also, it constructs the circuits with robust and reliable performance in digital designs. The objective of this paper is to design the proposed LFSR using the feedback polynomial function rather than the conventional bit-sliced function. The two DCVS strategies for the feedback polynomial function proposed are static and dynamic. The simulation results of LFSR has done, using the pyxis 130-nm IC design tool in the Mentor Graphics platform. The results demonstrated the low power dissipation in the circuits at various conditions of voltage levels. The high-speed DCVS designs of the proposed LFSR used fewer transistors with the optimistic less power dissipation. The static LFSR achieved 5.61 ?W and dynamic LFSR achieved 11.67 ?W at the chip voltage of 1.2 V. The layout generated in the IC station for the respective DCVS design shows that it occupied less area overhead

Published

2020-12-12

Issue

Section

Articles