Design of Ternary Logic Logarithmic Conversion Circuit with Error Correction Technique

  • Dr. R. V. Shalini, Dr. P. Sampath


This research work proposes the novel idea of designing CMOS VLSI based logarithmic conversion circuits for ternary values. As the most efficient radix for switching systems is the natural base (e = 2.718), stating the best radix is 3 rather than 2, Tri Valued Logic (TVL) is adopted in this paper for the design of ternary logic logarithmic conversion circuits. As logarithms simplify the complex repetitive arithmetic operations of DSP units by replacing multiplication process to mere addition, the application of logarithmic property to ternary logic values are analyzed in this research work. The use of logarithmic number system is often restricted on accuracy constraints, hence error correction procedures are proposed along with the conversion circuits. In this paper the logarithmic conversion circuits for 6, 11 and 21 ternary digit values are designed and the simulation results are compared for the same utilizing binary logic for corresponding 8,16 and 32 bit values.

Keywords-Tri Valued Logic (TVL);Ternay logarithms, Characteristic Value Identifying (CVI) circuit;Leading Trit Detecting (LTD) circuits; Logarithmic Error Correction (LEC) circuits.