Utilization Receptive Technology Mapping in Submicron Designs for Better Predictability in Power, Performance and Area
This paper presents a novel technology mapping algorithm for physical implementation of application specific integrated design. No preceding works facilitate the synthesis flow in the background of utilization factor. The physical layout estimation by prediction algorithms are pre-eminently focused on performance metrics with trade-off in standard cell density. This paper proposes a flow to accomplish maximal utilization factor up to 70% in the interim of synthesis phase by avoiding a feedback flow from placement and route tool with demanding performance, power and area.
Keywords-Technology mapping, ASIC, Netlist, Utilization, Netlist, FinFet and Physical Design.