IMPLEMENTATION AND ANALYSIS OF A LOW POWER AND HIGH SPEED COMPARATOR WITH CROSS COUPLED TRANSISTORS USING 180nm.

Abstract

A Comparator resembles a series arrangement of Amplifiers and gives high speed. It analysing for two arriving signals (V or I) and gives controlled digital limit esteem. A Voltage Comparator is faster speed than the generally valuable operational Amplifier used as a Comparator. In this paper, another Regenerative dynamic latch comparator with cross coupled transistors is implemented. In the proposed circuit it contains the positive feedback coalition is associated to the pre-enhancement circuit which lessens the kick back disturbance in the circuit. In this circuit it contains the NMOS switch which is associated between the differential circuits and furthermore it gives the rapid speed to the comparator. The proposed circuit will expend lower power and lesser delay of the circuit there by speeding up performance. The proposed circuit simulation results depend on gpdk180nm MOS technology model utilizing Cadence Virtuoso. The outcomes are clearly shows the approximately 50%delay saving, approximately 25% power saving, the speedy contain the 1.012 GHz and the PDP contains 0.116 Wsec.