Design And Analysis Of 10t Sram In Cmos Technology

Abstract

10T SRAM Cell is proposed to eliminate the soft errors. softerrors are nothing but the single node upsets that occurs in electronic devices, these are major reliability failure. soft errors can be eliminated by reducing the power, delay and SNM (static noise margin).10T SRAM has good read and write stability than the existing SRAM cell. By using the 10T SRAM cell,70%of the soft errors can be eliminated which increases The performance of the memory cell. The simulations are performed in 180 nm technology by using the cadence virtuoso tool 6.16 version, results shows that the 10T SRAM cell consumes less power, delay and SNM than the existing  12T SRAM cell.