A Novel Design Of Self Healing Technique To Increase The Testability And Optimze The Power Consumption

Abstract

For the reliability and lower the cost of manufacturing Built in self test are important for the processors to develop a highly reliable and error free circuits. So we a have proposed a new technique called self healing technique which reduces  the power consumption while testing the Chips. We also add pseudo random testing which decreases the chains in the testing. This improves the testability of the IC in which reduces the cost of the system. This is the best approach to increase the testability and also to decrease the cost of manufacturing of the IC. We have designed the model in Verilog and simulated in XILINX.