A Low Power Explicit Pulse-Triggered D Flip-Flop Based on Data Feed -Through Scheme.

Abstract

In this paper, a low power explicit pulse-triggered D flip-flop is proposed using data feed through scheme (DFTFF). This pulse triggered flip-flops are more popular than other conventional master-slave and transmission gate flip-flops. The proposed method Uses a modified true single phase clock latch structure and employs a data feed-through scheme to enhance the delay. The DFTFF flip-flop uses pull-up PMOS Transistors to control the input data to output data to reduce the power. The proposed circuit reduces the long discharging path in conventional explicit pulse-triggered flip-flops designs thereby increasing speed it is used for high speed applications. The proposed circuit simulation results are based on gpdk90nm CMOS technology model using Cadence Virtuoso.