Designing Of 64-Bit Risc Processor For Low Power Applications

Authors

  • G.VINDHYALAXMI ,K.NAGA KOUSHIL REDDY

Abstract

This paper presents a capable FPGA based low power pipelined 64-piece RISC processor with Floating Point Unit. RISC is an arrangement thinking where it reduces the unconventionality of the direction set, which will diminish the proportion of room, time, cost, power and warmth, etc.,. This processor is developed especially for Arithmetic assignments of both fixed and drifting point numbers, branch and reasonable limits. Pipelining would not flush when branch direction occurs as it is realized using dynamic branch gauge. This will construct stream in direction pipeline and high ground-breaking execution. In RTL coding one can diminish the dynamic power by using clock gating technique. In this paper moreover realize Double Precision floating point math undertakings like development, derivation, increment and division. This designing has gotten key and logically noteworthy in various applications like sign taking care of, outlines and clinical by using skimming point errands. The crucial code is written in the gear depiction language Verilog HDL.

Published

2020-10-16

Issue

Section

Articles