Efficient Binary Content Addressable Memory Cell Using Adiabatic Logic


  • Dr. PHV Sesha Talpa Sai, Dr. Amiya Bhaumik, Nikhil AC, Vinoth Kumar, Vivek M, Dr. M. Sucharitha


This paper describes about examination of powerand delay efficient of substance addressable memory core cells. By and large withplanof adiabatic cam, the storage array is worked by utilizing a CAM cell, yet analysis is donethrough various adiabatic logic formats. We proposed the structure of 3 unique addressable memory cells utilizing adiabatic logic, in particular Improved Efficient Charge Recovery Logic (IECRL) cam core cell, Improved Positive Feedback Adiabatic Logic (IPFAL)cam core cells and Improved Pass Transistor Adiabatic Logic (IPAL) cam core cell. Memory arraywith size 4x4 was designed and implemented utilizing the proposed power anddelay efficient of content addressable memory core cells in 32nm CNT FET advancement. It was discovered that recuperation of scattered power and delay produced by using CAM cells in CNTFET technology is better than CMOS technology. The simulation power and delay efficient of content addressable memory cells end up being better with power saving of98.5% and delay saving of 67.05% than the CMOS technology. The circuit was designed using 32nm CNTFET advancement with sinusoidal power clock of 1v, other node voltage at 0.9v utilizing H- spice