FPGA Architecture, Implementation and Optimization of Highly Linear Wideband Chirp Generation for FMCW Radar Application using Fractional-N PLL

Abstract

This work deals with theFPGAimplementationand improvementof Fractional-N Phase Locked Loops (Frac-N PLLs) which can be utilize for chirp’s waveform generation in the application of Frequency Modulated Continuous Wave (FMCW) radar. Fractional-N PLL have two key clock domains on which Fraction-N PLL work, first one is voltage-controlled oscillator clock domain and second is reference clock domain. In the digital system design, it is necessary to consider clock domain crossing in the system. In this we are analyzing the clock domain crossing for chirp generation system so that it will generate the chips which is more linear in nature. In addition, increases in the integer divide ratio during the generation of chirp.With increase in integer divide ration results inglitches in transient frequencywhich consequence the disruption in linearity of the generated chirps.So, we need to take care of integer division ratio such that generated chips linearity is maintained. In this paperwe suggest implementation practicesto overcomethese drawbacksin Fractional-N PLLs. The recommendedapproach can be utilizedfor the generation of wideband chirp which in linear in nature.Itis alsoused in distance accuracy and precision enhancement with the aspect of 1.5 and 1.0 respectivelyfor FMCW Radar distance measurement.