Performance Evaluation Of Approximate Adders For Image Processing Applications

Abstract

Efficient image processing is the fundamental requirement for real time
applications. Approximate computing has emerged as a solution for energy efficient image
processing design. This paper presents the performance evaluation of error tolerant adders for
image processing techniques using FPGA. MATLAB Simulink models have been developed
using Xilinx system generator tool. Spartan 6 has been chosen as the hardware platform.
Verilog modules have been developed to implement the approximate adder blocks. The
applications considered are image blending, image enhancement, contrast stretching,
histogram stretching and FIR filter implementation. The performance metrics for evaluation
are look up tables (LUTs), slices and PSNR. Based on the simulation studies, it has been
observed that the number of LUTs required is reduced up to 25% compared to conventional
adders. Also, the approximate adder proposed has 23% reduced gate count, 43% speed
improvement and 21.6% power reduction. Simulation results have been presented with
sample images.