The Design of Linear Phase Interpolator for 230MHz Power Private Network

Abstract

The existing open-loop phase modulator adopts a1 + a2 =1 to approximate a1
2 + a2
2 =1
mathematically. Therefore, it has the following three natural disadvantages: (1). The amplitude of the output
signal varies; (2). There is a deviation between the actual synthesis phase and the ideal one; (3). The DC
static working point of the output node is affected by the modulation signal. So linearity is not very ideal in
QPSK modulation. In order to overcome the defects of the existing phase interpolators, a new phase
interpolator circuit is designed by directly using the mathematical principle a1
2 + a2
2 =1. Limiting it doesn't
need triangle wave approximation, so the phase interpolator output signal amplitude constant. Secondly, this
ensures that the output node of the dc static working point is not affected by modulation signal. Third, it also
makes open loop linearity of the modulator ideal, and at the same time supports BPSK, QPSK, 16QAM, etc.
whose modulation method requires higher demands on linearity. Based on Grace 110nm CMOS technology,
this open-loop phase modulator circuit is realized, and the whole circuit layout area is only 0.2um2
; the
power consumption is 5.1mW, and the average phase step length is 0.703o
; DNL is 0.525LSB.