Study of Repeater Insertion Technique in Uniformly Segmented Global Interconnects

Authors

  • Nagarjuna Malladhi, Girish V. Attimarad

Abstract

This paper proposes a new repeater insertion technique in global interconnects which is based on transmission gates. The proposed repeater is inserted in uniformly segmented global interconnects, its power and performance is evaluated for the driver-interconnect-load system. The analysis is carried out for a long interconnect of 4mm length and the proposed repeater is inserted at a segmented length of 1mm and 2mm in two different cases. For a segmented length of 1mm, the propagation delay is 33.68% less and product-delay-product is 35.54% less as compared to on-chip interconnect scheme without repeater insertion. All the simulations of this work are carried-out using Cadence Generic PDK 45nm CMOS process with a supply voltage of 1V.

Published

2020-12-01

Issue

Section

Articles