Design of Low power Reversible Scan-Hold FlipFlop

Authors

  • V SHIVA PRASAD NAYAK , K MANJUNATHACHARI

Abstract

The manufacturing of a VLSI chip follows a series of procedures like chemical, optical and
metallurgical processes. The last stage of VLSI manufacturing is always testing, which separates the good
ICs from defective ones. Inadequate testing can lead to shipping of faulty chips to the customer. After
designing any chip it should be noted that testing should be done which can detect all the faults, the
development of test time and the execution test time should be kept as low as possible so that the design is
economical. Scan-hold is a design for testability (DFT) technique which allows to test a circuit keeping the
above mentioned factors in mind. This paper explains the design of reversible scan-hold flip-flop. The main
idea behind using the reversible logic instead of using conventional gates is to reduce the power dissipation
thereby increasing the efficiency of the circuit.

Published

2020-01-31

Issue

Section

Articles