High Speed Split Radix FFT Processor Using Wallace Tree Multiplier

Abstract

The problem of converting a time-domain signal into frequency-domain in an efficient manner is performed through DFT technique called Fast Fourier Transform (FFT) which is commonly used technique in the signal processing domain. Split-radix Fast Fourier Transform (SR-FFT) offers a better performance than traditional FFT techniques as number of complex multiplications are reduced. The proposed architecture is implemented in verilog code and synthesized using Xilinx ISE 14.7. Comparison of performance parameters of normal butterfly unit and butterfly unit with wallace tree multiplier in 1024-point SR-FFT is presented. The wallace tree multiplier implementation enhances the speed parameter that is frequency is improved over the normal butterfly unit. The implementation of1024 point split radix-FFT processor with shared memory architecture and Wallace tree multiplier at 111.162 MHz occupies 33473 flip-flops, 12323 slices and 49645 LUTs.

Keywords: FFT, SRFFT, LUT,DFT,DSP.