Design of Low Power 4-Bit Carry Look Ahead Adder Using Self Resetting and Gate Diffusion Input Logics

Abstract

Fast computation, low area and less power consumption are the key factors for any successful VLSI circuits. Most of the high speed computational devices are built with the help of combinational circuits. Adder which performs the addition process is the basic building block for any high level computational devices. Not only addition, an adder can be used to perform multiplication too. In that adder family,A Carry Look Ahead (CLA) adder is one of those basic and essential combinational circuits. Normally the CMOS dynamic logic combinational circuits consume more power because of the factors like charge leakage, charge sharing and loss of noise immunity. Hence to reduce the unwanted power consumption, we are designing a CLA circuit with the help of Self Resetting Logic (SRL) and Gate Diffusion Input Logic (GDI). These two logics are commonly known for the minimization of power consumption in the VLSI circuit design. In general the CLA adder is the fastest one in the computation process. Hence our proposed design will be the one, which is fast and consumes less power for the process of addition in any VLSI circuit.