Implementation of Peterson and Berlekamp Decoding Algorithms of BCH Error Correcting Code Based on FPGA

Authors

  • Zainab Abdullah Hassoun, Murtadha Jasim Hasan, Safa Isam Hakeem

Abstract

Channel coding is an effective tool in designing reliable digital communication system This paper considers the design and implementation of binary BCH (Bose, Chaudhuri, and Hocquenghem)  decoding algorithms for Peterson and Berlekamp error correcting code using a reconfigurable chip

Field  Programmable Gate Array (FPGA).  One of the most critical cyclic block codes is the BCH code.

The FPGA Design uses a parallelization so that the implementation is very quick (the calculation rate is high), and it can be simply modified. The BCH encoder and two different decoders is designed and simulated using Xilinx ISE and executed in FPGA. The BCH code of 5 bits data and 15 bits code word has been utilized. It can correct 3 bits error in any position of the 15 bits code word. The results indicate that the channel coding system operates very well and the Peterson decoding algorithm for (15,5) BCH code is very effective as it works faster and requires less logic components than Berlekamp decoding algorithm.

Published

2020-10-26

Issue

Section

Articles