Efficient Charge Recovery Adiabatic logic based 32-Multiply Accumulate (MAC) unit and FIR Half Band Filter using for DSP Applications

Abstract

The Multiply Accumulate (MAC) unitlies in the crital path of DSP and due to its high switching activity andhigh
performance requirement; it contributes to a major portion of the total power of DSP. Hence, it is essential to focus
attention on lowering theMAC unit power consumption in particular along with area and speed. In this work, 32 bit
MAC unit is implemented using ECRL Adiabatic logic that promises a significant reduction in power consumption.
The proposed 32 Bit ECRLMAC unit is designed and simulated in the TANNER EDA tool for 22 nm technology.
Performance parameters like power area, delay are measured for proposed MAC unit and compared with
conventional CMOS for different operating frequencies and temperatures for a supply voltage of 1.5 V. For the
proposed ECRL MAC unit it is observed that, it has 23% less PDP at 300C and frequency of 1000MHz compared to
convention CMOS design respectively. In this paper, a novel l7, 17,31 FIR Half Band Filter (HBFs) are proposed
and implemented using the proposed ECRL MAC unit for DSP multi-rate applications and simulated at 250MHz and
1000 MHz for 22 nm technology respectively. It is observed that when compared with the recent works of MAC unit
in literature proposed FIR HBFs have better performance. So, it is concluded that the proposed ECRL MAC unit and
FIR HBFs can be effectively used in DSP multi-rate signal processing applications.